OLIX, a London chip startup founded in 2024, raised $312M in a Series B at a $3.3B valuation on 3 August 2026, and its pitch is unusually specific: build AI inference silicon that uses no high-bandwidth memory and no advanced packaging at all. Instead of stacking HBM beside a large general-purpose die, OLIX photonic AI chips keep model weights in on-chip SRAM and move data between dies with light rather than copper. If the approach works, it sidesteps the two most supply-constrained parts of the AI hardware stack; if it does not, the company has bet a very large valuation on a memory architecture that has historically struggled with capacity.
TL;DR
- OLIX (formerly Flux Computing) raised $312M at a $3.3B valuation, announced 3 August 2026, up from roughly $1B in February 2026 after a $220M Series A.
- PitchBook and DataCenterDynamics both describe it as the largest semiconductor venture round raised in Europe.
- Fundomo led. Arm and Hudson River Trading participated, Reed Hastings invested as an angel, and the UK government's Sovereign AI venture fund took part.
- The first product, DX-1, is a decode accelerator claiming more than 10,000 tokens per second per user on 100B-parameter models, with first customer deliveries targeted for H2 2027.
- The architecture uses SRAM instead of HBM, no advanced packaging, and a "slow and wide" optical interconnect linking up to 10,000 chips in a single scale-up domain.
- Everything here is a vendor claim about unshipped silicon. There is no independent benchmark yet.
What exactly did OLIX raise, and who backed it?
The round is $312M of primary capital at a $3.3B post-money valuation, announced by the company on 3 August 2026. That is roughly a tripling of the ~$1B valuation attached to its $220M Series A in February 2026, six months earlier. PitchBook and DataCenterDynamics both frame it as the largest chip-sector venture round in European history.
Fundomo led. The participant list is the more interesting signal: Arm, which sells the CPU IP that most of the industry's inference hosts run on, and Hudson River Trading, a firm whose day job is latency-sensitive compute. Reed Hastings came in as an angel. Every existing investor increased its commitment, including Hummingbird Ventures, Crane, Plural, Creandum, Phoenix Court and Transition. The UK government's Sovereign AI venture fund also invested, which is the part that will get cited in policy documents. UK AI Minister Kanishka Narayan summarised the rationale bluntly: countries that build chips build leverage. That framing sits close to the argument we made in AI investment strategies: leverage versus long-horizon bets.
Two hires matter as much as the money. Professor Nick McKeown joined the board — co-inventor of software-defined networking, OpenFlow and P4, Stanford Professor Emeritus, 2025 Marconi Prize winner, and co-founder of both Nicira (acquired by VMware) and Barefoot Networks (acquired by Intel). Matt Briers joined as CFO after nine years as CFO of Wise, where he ran the 2021 direct listing on the London Stock Exchange at an £8.75B valuation. That is a board and finance function built for a company that expects to be scrutinised.
Why does eliminating HBM matter so much?
High-bandwidth memory is the tightest bottleneck in AI hardware. A single supplier, SK Hynix, held roughly 58% of the HBM market as of mid-July 2026, and HBM allocation now effectively determines how many accelerators any vendor can ship in a given quarter. Advanced packaging — the CoWoS-class processes that bond HBM stacks to a logic die — is the second chokepoint, and it is similarly concentrated.
OLIX's answer is to not participate in either market. Weights live in fast on-chip SRAM, so there is no HBM stack to buy and nothing to bond. The tradeoff is obvious and worth stating plainly: SRAM is fast but small. A design that holds a 100B-parameter model in SRAM has to spread that model across a lot of silicon, which is exactly what OLIX proposes.
The supply-chain angle is not abstract. Capacity constraints are already shaping which models get built and how quickly, a dynamic covered in the chip bottleneck behind the next frontier models, and the packaging layer is drawing new regional investment such as the ASIP OSAT facility in Vizag.
How does the X-1 platform and DX-1 chip actually work?
OLIX's organising metaphor is that a datacentre is a factory whose product is the token, and that each stage of that factory deserves purpose-built machinery rather than one generalist machine doing every step. Prefill, decode and the surrounding stages have genuinely different compute-to-memory profiles, and today they all typically run on the same GPU.
The X-1 platform unrolls a model fully across many specialised chips, forming something closer to a production line than a pool of interchangeable accelerators. Each chip holds its assigned layers in SRAM permanently, so there is no repeated weight streaming from external memory. Between dies, OLIX uses what it calls a "slow and wide" optical interconnect: many parallel light-based lanes at modest per-lane rates rather than a few very fast copper links, which trades clock speed for energy per bit and distance. Up to 10,000 chips can be joined in one multi-rack scale-up domain, scheduled by a fully deterministic compiler — deterministic scheduling being the natural fit for a pipeline where every chip's role is fixed at compile time.
DX-1 is the first product: a decode accelerator aimed at the reasoning and generation stage. The headline claim is more than 10,000 tokens per second per user on 100B-parameter models, with the architecture said to scale to 10 trillion parameters and beyond. Delivery to first customers is targeted for the second half of 2027.
What would this change about inference economics?
Decode throughput per user is the number that governs how a reasoning model feels to use and how much a long chain of thought costs to serve. Per-user speed of that order would make long reasoning traces cheap enough to use by default rather than reserve for hard queries, which is the pressure point behind the 2026 inference cost war and the pricing squeeze from Chinese open-weight models.
There is a second-order effect on infrastructure. Optical die-to-die links and no HBM stacks change the power and thermal profile of a rack, which matters as data centre tax breaks get repealed and total cost of ownership faces closer inspection. It also feeds the broader market question of whether AI capital spending is producing proportional returns, which we examined in why tech stocks are falling despite record AI spending.
What are the honest limitations here?
Four, stated directly.
The silicon has not shipped. Every performance figure is a vendor claim about a chip due in H2 2027, unaudited by any third party and not measured under MLPerf or comparable conditions.
SRAM capacity is the hard constraint. Holding large models entirely on-chip requires a great deal of die area across many chips, so the economics depend on how well the aggregate wafer cost compares with a smaller number of HBM-equipped GPUs.
Specialisation cuts both ways. A decode-only accelerator needs something else to handle prefill, and a fully unrolled pipeline is efficient for the model it was compiled for while less flexible when architectures shift.
Software is usually the gating factor. CUDA's maturity has defeated better-on-paper hardware repeatedly, and a deterministic compiler for a 10,000-chip pipeline is a substantial engineering commitment in its own right.
FAQ
Q: How much did OLIX raise and at what valuation? A: $312M in a Series B at a $3.3B valuation, announced 3 August 2026 — up from ~$1B in February 2026 after a $220M Series A.
Q: What does HBM-free actually mean for an AI chip? A: Weights live in on-chip SRAM rather than HBM stacks, so the chip needs neither HBM supply nor advanced packaging. The tradeoff is much lower memory capacity per chip, offset by spreading the model across many dies.
Q: What is the DX-1 and when does it ship? A: DX-1 is OLIX's first chip, a decode accelerator for the generation stage of inference. The company targets first customer deliveries in the second half of 2027 and claims more than 10,000 tokens per second per user on 100B-parameter models.
Q: Why are photonic interconnects used instead of copper? A: Light carries data between dies with lower energy per bit and less signal degradation over distance. OLIX runs many parallel optical lanes at modest speeds — "slow and wide" — suited to linking thousands of chips in one domain.
Q: Was the UK government really an investor? A: Yes. DataCenterDynamics confirmed that the UK's Sovereign AI venture fund participated in the round, alongside Arm, Hudson River Trading and angel investor Reed Hastings.
Q: Does this threaten Nvidia? A: Not in this product cycle. Nvidia's advantage is a mature software stack and installed base, and OLIX has no shipping silicon until 2027. The near-term threat is narrower: pressure on specific inference workloads where decode throughput per user dominates cost.
The bottom line
OLIX has raised European record money on a coherent structural argument — that inference is a pipeline of distinct stages and the industry is running all of them on one generalist chip tied to the scarcest component in the supply chain. The board and CFO hires suggest a company preparing for real scrutiny rather than a research project. Judgement should wait for measured DX-1 silicon in 2027, and for evidence that the compiler and software stack are ready when it arrives.
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